Field of the Invention
The present invention relates to a processing apparatus and a device manufacturing method.
Description of the Related Art
An exposure apparatus used to manufacture a semiconductor device includes a wafer conveying hand that supplies/collects a wafer to/from a wafer stage, a pre-alignment stage, a wafer stage, and a conveying robot that conveys a foreign substance removing member for a wafer chuck. The pre-alignment stage aligns a wafer using a notch or an orientation flat before moving the wafer to the wafer stage. The wafer stage holds and conveys the wafer by vacuum chuck. The surface shape of the wafer vacuum-chucked by the wafer chuck and held on the wafer stage is measured using a focus sensor. The wafer surface is located at the focus position based on the shape, and exposure is performed.
Presently, a stepper that performs cell projection by reducing a conventional almost square exposure region and projecting it onto a wafer and a scanner that accurately exposes a large screen by relatively scanning a reticle and a wafer at a high speed, using an exposure region formed into a rectangular slit shape are used as the exposure apparatuses. Alignment between the reticle and each shot on the wafer is done by optically detecting the positions of alignment marks corresponding to the respective shots, which are exposed and transferred to the wafer at the same time as the circuit pattern on the reticle, and positioning the wafer with respect to the reticle based on the detection result. Normally, AGA (Advanced Global Alignment) is performed. AGA is an alignment method of moving the wafer stage to the exposure position based on statistical estimation calculation by the position information of a plurality of alignment marks. Selection of the alignment marks to be used for AGA measurement is constant independently of the shape of the wafer.
Along with an increase in the integration degree of semiconductor devices, micronization and multilayering of interconnections are proceeding. The multilayered structure of interconnection layers causes a phenomenon in which film distortions that have occurred during deposition accumulate and warp the whole wafer later in the semiconductor manufacturing process. In the TSV (Through Silicon Via) process that is a stacking technique for a semiconductor chip, the difference in the thermal expansion coefficient between the metal (for example, copper) of a through electrode and the ambient silicon causes a distortion between the silicon and the through electrode metal. A wafer may warp due to this distortion. Failing in coping with the warping amount of the wafer, an error may occur in vacuum chuck of the wafer chuck, and the sequence may stop. When the wafer warps, a local distortion occurs in the wafer on the wafer chuck, affecting AGA measurement or scan exposure.
Japanese Patent Laid-Open No. 2001-284434 discloses a wafer conveying robot including a periphery pressing member configured to correct the warp of a wafer. Japanese Patent Laid-Open No. 2003-234392 also discloses a wafer conveying mechanism including a pressing plate configured to correct the warp of a wafer.
In the apparatuses described in Japanese Patent Laid-Open Nos. 2001-284434 and 2003-234392, however, since the periphery pressing member or pressing plate configured to correct the warp of the wafer is provided on the wafer conveying robot, the weight of the object conveyed by the robot increases. Hence, when no chuck error exists, it is difficult to convey the wafer at a high speed and accuracy. In addition, when correcting the warp of the wafer by the periphery pressing member or pressing plate to cope with a chuck error, subsequent wafers cannot be prepared. Hence, the lot processing takes a long time.